arm designs mp cores and cached macrocells for its licensees. some partners offer arm core in embedded products for vertical markets. the arm cores and cached macrocells implement a load/store architecture and have 31 general-purpose registers with 16 simultaneously visible. a fast interrupt has a minimum latency of four processor cycles and uses seven private […]

uC/OS-II is a low cost commercial Priority based Preemptive Real-Time kernel. It has ports for most of the popular processor & boards in the market. I ported it to ARM & MIPS 4K architectures.
Ports :
ARM port for uC/OS-II
The latest release, ver 1.16 of the ARM (7TDMI, 720T, 920T) port for uC/OS-II V2.61 (and higher) […]

Shenzhen-based Embest Info & Tech has created an embeddable two-board sandwich that combines a tiny ARM9 daughtercard with a “PC/104-compliant” carrierboard. The EM104V1 obtains the bulk of its functionality from the tiny Mini2410-III CPU card, which in turn relies on a highly-integrated Samsung microcontroller.
(Click for larger view of the EM104V1 PC/104 sandwich)
According to Embest, the […]

http://www.arm.com/ Professional information about ARM microcontrollers;
http://www.codesourcery.com/gnu_toolchains/arm.html develops improvements to the GNU Tool-chain for ARM processors and provides regular, carefully tested, pre-compiled releases of the GNU Tool-chain;
http://www.EmbeddedArtists.com/ Ships pre-setup GCC build environment with all their Quick-Start Boards/Kits;
http://www.embedinfo.com/ Embest IDE for ARM, include Compiler,debugger,editor,project manager,flash programmer,JTAG Emulator, Low cost;
http://www.iar.com/ Embedded Workbench for ARM7,9,11 C/C++ compiler;
http://www.keil.com/ IDE,Debugger,Simulator which […]

With its multicore/multiprocessor support, ARMv7 can now handle cache coherency.
William Wong??
Article Rating: Not Rated
ARM’s new symmetric multiprocessing (SMP) multicore architecture has found a home in the popular ARMv7 architecture. SMP is similar to the architecture found with ARM’s higher-end cores.
However, the new architecture handles up to four cores plus support for accelerator and DMA […]