Given the surging importance of power in today’s shrinking technologies, low-power verification is taking on a vital role. Design teams can no longer afford to just worry about dynamic power. They have to pay close attention to leakage power as well. Thus they have to implement power reduction methodologies at the system architectural stage. Here […]

?Introduction

By Jon Stokes??
One of the greatest challenges facing the designers of many-core processors is resource contention. The chart below visually lays out the problem of resource contention, but for most of us the idea is intuitively easy to grasp: more cores and more simultaneous threads means more contention for shared resources, specifically cache space and […]

By closely coupling analog/RF design and foundry support, designers gain greater assurance of successful system-on-a-chip integration.
———————–
By Albert Yen
Designers tasked with creating the analog/radio-frequency (RF) portion of system-on-a-chip (SoC) products face a considerable array of challenges. For example, different design considerations and architectures are required by system specifications within varying operating frequencies, transmission methods, digital modulations, […]

 
Semicon West: Foundries are diverging in their approaches to high-k dielectrics at the 45-nm process node.
By Ron Wilson, Executive Editor — EDN
Even as many design teams are contemplating the move from 130-nm to 90-nm technology, at the Semicon West conference in San Francisco this week the world begins at 45 nm. Equipment and materials vendors […]

The Verilog HDL is an IEEE standard hardware description language. It is widely used in the design of digital integrated circuits.

Here we provide some useful background information and a tutorial, which explains the basics of Verilog from a hardware designer’s perspective. We also provide some useful tips and pointers to other Verilog information on the […]